Heterogeneous Integration, IC Packaging and Testing

NA

College of Design and Engineering (CDE)

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Objectives

At the end of the courseparticipants will understand the concept of heterogeneous integration in semiconductor, and have good knowledge on IC packaging and testing.



Who Should Attend

IC Packaging/ Testing




Entry Requirements

Bachelor degree or equivalent




Class Schedule

Mondays 6pm to 9pm




Tutorial Schedule

Same day as lecture




Lesson Delivery

Lectures, 2 assignments (50%), final exam (50%).




Full Fees (before GST)

S$5800.00




Nett Fees payable after SSG Funding



NA


** Please note that the mode of delivery is subject to change in light of the COVID-19 situation. Courses marked ‘online’ may have compulsory face-to-face sessions such as laboratory or hands-on components and details should be sought from the schools or departments before learners register for them.

Last updated: 26 September 2024

Upcoming Course Dates
TBC

Delivery Mode**
Face-to-Face

Course Code
EEK5102

Funding Type
SSG Funding
Eligible for SkillsFuture Credit (SFC)
Alumni eVoucher (L3)

Type
Modular Course

Stacks/ Bundles to
MSc in Semiconductor Technology and Operations

Audit/Graded
Graded

Area of Interest
Electrical & Electronics Engineering