Integrated Circuit Technology and Design Methodology

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College of Design and Engineering (CDE)

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Objectives

Knowledge and understandingHaving successfully completed the course, students will be able to understand:
  • Challenges in very deep submicron billion gate design;• Major process technologies used in current designs;• Most important approaches for modern IC design;• Difference between SoC and SiP;• Motivation behind SoC and SiP designs;• Major cost in development of modern SoC/SiP solutions.Subject specific intellectual skillsHaving successfully completed the course, students will be able to:• Understand major process steps in building MOSFET transistors;• Appreciate the advantages of design reuse;• Identify the importance of hardware/software co-design, clock and low power design;• Appreciate the significance of leakage current, design for manufacturability, testability and chip reliability;• Realise the role of Electronic Design Automation (EDA) tools in IC design;• Distinguish the various tasks and personnel required in SoC/SiP design project;• Appreciate the design flow of an Application-specific Integrated Circuit (ASIC) chip and the complexity and challenges of VLSI physical design.Subject specific practical skillsHaving successfully completed the course, students will be able to:• Demonstrate knowledge of the major steps in ASIC chip construction;• Explain the characteristics of good design flow and identify the two major aspects of ASIC design flow;• Recognise the important steps in cell-based ASIC design methodology;o System-level study;o RTL system level description;o Functional verification;o Logic synthesis;o Physical synthesis;• Demonstrate knowledge in the processes related to VLSI physical;o Floor planning;o Placement;o Routing;o Power network;o Clock network;o Design for testability (DFT);o Parasitic extraction and delay calculation;o Signal integrity;o Verification;o Tapeout.



Who Should Attend

IC Packaging/ Testing




Entry Requirements

Bachelor degree or equivalent




Class Schedule

TBC




Tutorial Schedule

Same day as lecture




Lesson Delivery

Lectures, 2 assignments (50%), final exam (50%).




Full Fees (before GST)

S$5800.00




Nett Fees payable after SSG Funding



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** Please note that the mode of delivery is subject to change in light of the COVID-19 situation. Courses marked ‘online’ may have compulsory face-to-face sessions such as laboratory or hands-on components and details should be sought from the schools or departments before learners register for them.

Last updated: 14 April 2025

Upcoming Course Dates
11/08/2025

Delivery Mode**
Face-to-Face

Course Code
EEK5101

Funding Type
SSG Funding
Eligible for SkillsFuture Credit (SFC)
Alumni eVoucher (L3)

Type
Modular Course

Stacks/ Bundles to
MSc in Semiconducto Technology and Operations

Audit/Graded
Graded

Area of Interest
Electrical & Electronics Engineering